The subject system and method are generally directed to cancelling voltage offset effects encountered of electronic circuits during operation. More specifically, the subject system and method provide pre-compensation for such effects at one or more inputs of electronic circuits, and do so in a manner that productively harnesses the normally unwanted stray effects of parasitic capacitance.
The ongoing trend towards increasingly smaller geometries in the integration of electronic circuits enables greater capabilities, but also presents greater challenges to proper implementation and use. Extremely high speed circuit designs are made possible by high speed transistor devices integrated with increasingly shorter channel lengths. These circuit designs are typically laid out and printed on substrates using electronic design automation (EDA) measures. They require smaller loading (lower input impedance levels) to minimize power consumption and maximize bandwidth for given applications. The minute device geometries involved in these applications lead to so-called offsets in certain operating parameters whose values should ideally match for optimum circuit performance.
These parametric offsets may be due in different degrees to various factors, including manufacturing process mismatch and other errors/distortions due to non-ideal realization of given systems. An offset in terms of voltage reflects the systematic distortion of an electronic circuit's response to an input signal(s). The offset is said to be ‘input referred’ when the offset is expressed in terms of the deviation required in the circuit's input voltage for an ideal/noiseless version of the circuit to produce the same distorted response.
Such offsets are increasingly troublesome for applications involving faster switching/operating speeds and smaller device geometries. They necessitate costly tradeoffs, especially in systems employing certain types of circuits which by virtue of their architectural features and component make up are particularly vulnerable to offset effects. Systems employing comparator circuits, for instance, are known to have considerable voltage offset. Consequently, systems such as SerDes (so-called serializers/deserializers) must commit more of their error budgets to voltage offsets. Especially at heightened serial link speeds necessitating greater front end gain, the resulting offsets consume excessively large portions of the vertical eye opening. In so-called data slicer systems designed for high speed operation the offset typically consumes up to 10-20 percent of the vertical eye opening budget.
In comparator circuits employed by these and other high speed applications, voltage offset causes the signals received at the circuit's compared inputs to be ‘seen’ shifted in difference by that voltage offset amount. As a result, two input signals of like voltage may be taken mistakenly by the comparator circuit as having a voltage difference when none actually exists. The mistaken shift constitutes the circuit's voltage offset.
An input referred voltage offset of an electronic circuit encountered at an input of that circuit may be compensated for by applying a voltage adjustment sufficient in amplitude and polarity on the input signal there sufficient to cancel the voltage offset. Yet, accomplishing this without excessively encumbering implementation and operational factors has heretofore remained a challenge.
Attempts have been made in the art to cancel voltage offset in comparator circuits. In one known approach, illustrated in FIG. 8, a bank of active devices are employed to inject a selected amount of current to the drain of the field effect transistor (FET) serving as the input sampling switch at each input stage. But this approach is notably prone to considerable temperature drift during system operation. Also, the numerous active devices employed in the multiple current injection stages at each of the input switching transistors not only increase physical size which consumes precious chip area, they present numerous gates and heavy clock signal loading which consume considerable power.
There is therefore a need for a system and method for simply yet effectively compensating for input referred voltage offset of an electronic circuit without excessive temperature drift, large size, undue loading, or other such drawbacks.